1. Field of the Invention
The present invention relates to a method for forming a gate and etching a conductive layer, and more particularly, to a method of etching polysilicon and silicon oxide by utilizing a patterned silicon nitride layer with high hydrogen concentration as a hard mask, and removing the patterned silicon nitride layer utilizing a low-temperature phosphoric acid solution, so as to remove the patterned silicon nitride layer without damaging the structures of polysilicon and silicon oxide.
2. Description of the Prior Art
Metal-oxide-semiconductors (MOS) are important electronic devices in the fabrication of integrated circuits. As the sizes of semiconductor devices become smaller and smaller, MOS fabrication is constantly enhanced for fabricating MOS devices with smaller sizes and higher quality. Due to the miniaturization, it is more and more important to prevent the fabrication processes from damaging the gate dielectric layers of MOS devices.
Please refer to FIG. 1 through FIG. 4. FIG. 1 through FIG. 4 are schematic diagrams showing the common means of fabricating a gate utilizing a patterned hard mask. As shown in FIG. 1, a substrate 12 is provided, including a dielectric layer 14, a conductive layer 16, a mask layer 18 and a photoresist layer 24 on its surface in order. The dielectric layer 14 usually includes silicon oxide, and the conductive layer 16 includes doped polysilicon. Subsequently, as shown in FIG. 2, the photoresist layer 24 is patterned by an exposure-and-development process. As shown in FIG. 3, the mask layer 18 is etched to become a patterned hard mask 18a by utilizing the patterned photoresist layer 24 as an etching mask, and the photoresist layer 24 is removed by an ashing process. Next, as shown in FIG. 4, the conductive layer 16 and the dielectric layer 14 are etched by utilizing the patterned hard mask 18a as an etching mask so as to form a gate 26. The patterned hard mask 18a is removed thereafter to form the gate structure of a MOS.
As known by those skilled in this art, after forming a gate structure on a substrate, a lightly doped drain (LDD) is formed on the two corresponding sides of the gate structure. Next, a spacer is formed on the sidewall of the gate structure and an ion implantation process is performed to form a source/drain region within the substrate by utilizing the gate structure and spacer as a mask. Finally, a silicide material is often formed over the surface of the gate structure and the source/drain region to improve the ohmic contact between the contact plugs and the gate structure and the source/drain region.
Nevertheless, the process of removing the patterned hard mask 18a causes some problems. Please refer to FIG. 5. FIG. 5 is schematic diagram showing a traditional gate formed by utilizing oxide or oxynitride as a patterned hard mask. The traditional process utilizes oxide or oxynitride as a patterned hard mask and removes the patterned hard mask by diluted hydrofluoric acid. As shown in FIG. 5, because the diluted hydrofluoric acid could etch oxide with a high rate, the diluted hydrofluoric acid also etches the dielectric layer 14 that includes oxide during the process of removing the patterned hard mask. Thus, defects, such as the undercut effect, may be caused in the dielectric layer 14, and the device reliability is decreased.
In consideration of the previous problem, the prior art uses silicon nitride as the material of the patterned hard mask 18a. Please refer to FIG. 6. FIG. 6 is schematic diagram showing a gate formed by utilizing silicon nitride as a patterned hard mask according to the prior art. In the prior art, the semiconductor substrate is immersed in a phosphoric acid solution at 155° C. to 170° C. in an etching tank, so as to remove the patterned hard mask including silicon nitride. However, as shown in FIG. 6, the hot phosphoric acid solution also etches and damages the surface of the conductive layer 16 including polysilicon during the process of removing the patterned hard mask. This causes defects in the shape or the surface condition of the gate 26, and decreases the quality of the resulting salicide. Thereafter, the high electric resistance may be caused in the gate 26, and may influence the operation of the gate 26.
In order to prevent the polysilicon conductive layer from being affected by the hot phosphoric acid solution, a technology of using a lower temperature phosphoric acid solution to remove the silicon nitride mask is being developed. However, because silicon nitride is quite chemically stable, the removal rate of the silicon nitride mask is very slow when utilizing the lower temperature phosphoric acid solution. Thereafter, the etching process takes a long time, increases the cost, and cannot remove the hard mask well enough.